This invention pertains to a type of processing of the variable-length code based on image signals, etc. In particular, this invention pertains to the sorting of a variable-length code for use in the coding of MPEG.
In the MPEG standard, in order to realize high-efficiency coding, the variable-length code is adopted. The variable-length code is adopted for coding at a high efficiency for transmitting the quantized DCT coefficient. By giving shorter codes to symbols having a high probability of generation and longer codes to symbols having a low probability of generation, it is possible to reduce the amount of the data transmitted.
For the prior art pertaining to the output of the variable-length code, as shown in FIG. 1, the serial bit from parallel/serial converting unit 3 to serial/parallel converting unit 4 is taken as an input to control logic unit 2; when it becomes equal to the magnitude of the xe2x80x9clength,xe2x80x9d the next data portion is input from FIFO 1 to parallel/serial converting unit 3. In this case, when it is impossible to perform the processing of parallel/serial converting unit 3 and serial/parallel converting unit 4 more than 28 times faster than the input clock of the code/length, it is naturally necessary to set a buffer such as FIFO 1 in the former stage of parallel/serial converting unit 3. That is, the processing rate of parallel/serial converting unit 3 and serial/parallel converting unit 4 becomes a restriction of the processing rate of the entire system containing them.
According to this invention, sorting of the variable-length code means that, as shown in FIG. 2, the effective data among the 28-bit code (with its length represented by xe2x80x9clengthxe2x80x9d) is extracted and packed as shown in FIG. 3, and is output at the time when it becomes a prescribed length. That is, the effective portion of the code is accommodated in a buffer (FIG. 3(a)), the initial code of the buffer corresponding to the length of the next code is shifted, and the code is accommodated in the buffer (FIG. 3(b)); this operation is repeated until the buffer becomes full and is output (FIG. 3(c)). In the sorting, the code is moved one bit at a time to the buffer and, at the same time, it is shifted one bit by one bit in the buffer. An improvement is demanded from the viewpoint of the processing rate.
This invention provides a type of sorting device for a variable-length code containing the following parts: a coding part that converts the length value to a first bit column according to its value, a first shifter that converts the first bit column input from the aforementioned coding part to a second bit column according to the shift parameters, a second shifter that converts the code value to a third bit column according to the shift parameter, and a register that has the second bit column input from the aforementioned first shifter and the third bit column input from the aforementioned second shifter, and which outputs only the content of the bit at the position of the third bit column corresponding to the position of the bit indicating the prescribed value of the second bit column.